一句话：提出 FpgaFlow，首个用 FPGA 专用硬件加速过程内集合式数据流分析的设计，借助分配性实现线性空间可扩展并取得平均 12–15 倍加速。
集合式（位向量）数据流分析是众多静态分析任务的基础构件，已有加速工作都从软件角度出发，借助多核 CPU、GPU、分布式系统等通用计算平台，而以硬件为中心、直接设计专用硬件来加速数据流分析的方向尚属空白。本文出于研究探索的目的，尝试用高度可定制、适合快速原型化领域专用硬件的 FPGA 来实现数据流分析，并首先聚焦广泛使用的过程内分析。作者发现，即使是这一场景，直接用 FPGA 实现经典 worklist 算法也不可行：其空间复杂度随过程规模超线性增长，很快耗尽 FPGA 有限的高速片上存储。为此提出 FpgaFlow：(1) 利用集合式数据流分析的分配性，把空间需求降为随过程规模线性增长，从而突破空间可行性瓶颈；(2) 通过硬件特有的并行性——带数据转发的流水线以及 BRAM 分区与复制——加速分析。在多个流行 Java 真实项目（平均 32.5k GitHub stars）上，用活跃变量与到达定值两种分析进行评估：FpgaFlow 与最先进的 Java 静态分析器 Tai-e 结果完全一致（合计 750 亿比特），并在仅 55 MHz 的 Xilinx Zynq-7020 上相比运行于服务器级 CPU（2.20–3.00 GHz）的 Tai-e 分别取得平均 15.45x 和 12.32x 的加速。
Set-based (a.k.a. bit-vector-based) dataflow analysis is a fundamental building block for many static analysis tasks, and significant effort has been devoted to accelerating it. Existing acceleration approaches address the problem from a software perspective, leveraging various general-purpose computing platforms, such as single- and multi-core CPUs, GPUs, and distributed systems. In contrast, a hardware-centric approach—designing specialized hardware that directly accelerates dataflow analysis—remains unexplored. Motivated by this gap and out of pure research curiosity, we conduct a preliminary exploration of designing specialized hardware for dataflow analysis using FPGAs, which are highly customizable and well suited for rapidly prototyping domain-specific hardware. As a first step toward hardware-accelerated dataflow analysis, we focus on the widely used intra-procedural dataflow analysis. However, we find that designing specialized hardware even for this setting is already challenging: a straightforward FPGA implementation of the classical worklist algorithm is infeasible, because its space complexity grows superlinearly with procedure size, quickly exhausting the FPGA's limited high-speed on-chip memory when analyzing large procedures. To address this challenge, we introduce FpgaFlow, a specialized hardware design for dataflow analysis that (1) overcomes the spatial infeasibility challenge by leveraging the distributivity of set-based dataflow analysis to achieve linear spatial scalability, and (2) accelerates analysis through hardware-specific parallelism—pipelining with data forwarding and BRAM partitioning and replication. We evaluate FpgaFlow on diverse and popular real-world Java projects (averaging 32.5k GitHub stars) using two representative dataflow analyses—live variables and reaching definitions—and compare it against their software implementations in a state-of-the-art Java static analyzer Tai-e. In terms of correctness, FpgaFlow produces exactly the same analysis results as Tai-e, amounting to 75 billion bits. In terms of acceleration, even on a modest Xilinx Zynq-7020 FPGA (55 MHz), FpgaFlow achieves an average speedup of 15.45x for live variables and 12.32x for reaching definitions compared with Tai-e running on a server-grade CPU (2.20 GHz to 3.00 GHz). We hope this work offers useful insights toward future FPGA-accelerated static analysis.
@article{paperbot12150,
title = {When FPGA Meets Dataflow Analysis: An Explorative Step},
author = {Fang Wei and Qinlin Chen and Nairen Zhang and Jiacai Cui and Tian Tan and Zhiqiang Zuo and Yue Li},
journal = {Proceedings of the ACM on Programming Languages},
volume = {10},
number = {OOPSLA2},
year = {2026},
doi = {10.1145/3839508}
}