一句话：提出智能体框架 Spec2V，用双层思维树规划与验证驱动调试将规范自动生成 Verilog 代码。
针对 FPGA 设计中自然语言规范到 Verilog 代码的自动化生成，现有 LLM 方法受限于线性推理与硬件并行逻辑之间的语义鸿沟，难以分解复杂任务、生成低资源代码并修复仿真错误。本文提出智能体框架 Spec2V：其一，采用双层 Tree of Thought 规划，将复杂规范解耦为宏观拓扑与微观逻辑结构，抑制逻辑漂移并提升初始解正确率；其二，在验证调试阶段将失败分析重构为结构化归因任务，以 LLM-as-a-Judge 结合多源证据定位仿真错误来源；同时引入多温度对冲采样与波形失配率过滤，从大量候选中高效识别正确实现。在 VerilogEval Machine 与 Human 基准上 Pass@1 分别达 99.8% 与 99.4%，RTL 案例研究显示其显著减少人工实现与迭代工程开销。
Field Programmable Gate Array (FPGA) is essential in mission-critical fields like aerospace. It offers high flexibility and deterministic real-time response. With the increase in development demands and system complexity, the traditional design paradigm that relies on manual expertise has become inefficient. Although large language models (LLMs) provide a potential pathway for automated code generation, a significant semantic gap remains between the linear reasoning patterns of LLMs and the inherent parallelism of FPGA hardware logic. Current methods encounter difficulties in decomposing complex tasks, low-resource code generation, and resolving simulation errors. To address these issues, we present Spec2V, an agent framework for the generation of Verilog code. Spec2V incorporates two key complementary components: (i) we propose a task planning method based on a dual-layer Tree of Thought. It decouples complex specifications into macro-topology and micro-logic structures to mitigate logical drift from linear reasoning and to improve the accuracy of initial solutions. (ii) During validation and debugging, Spec2V reformulates failure analysis as a structured attribution task with an LLM-as-a-Judge paradigm. It utilizes the reasoning capabilities of LLMs and multi-source evidence to localize the sources of simulation errors. Furthermore, the framework introduces a multi-temperature hedged sampling strategy and a waveform mismatch rate filtering mechanism to identify correct implementations efficiently from extensive candidate spaces. On the public VerilogEval Machine and Human benchmarks, Spec2V achieves Pass@1 accuracies of up to 99.8% and 99.4%, respectively. Case studies on representative RTL design tasks further demonstrate that Spec2V significantly reduces the manual effort required for implementation and mitigates the overhead of iterative engineering through closed-loop planning, validation, and debugging.
@inproceedings{paperbot12466,
title = {Spec2V: Planning-Guided Specification-to-Verilog Generation Framework with Verification-Driven Debugging},
author = {Xuming Liu and Chi Zhang and Jinglong Xu and Shan Zhou and Jinbo Wang},
booktitle = {ASE},
year = {2026},
doi = {10.1145/3832783.3834342}
}