一句话：Filament 用时间线类型静态描述并检查硬件的时序与结构约束，实现模块安全组合与正确流水线化。
模块化设计是硬件模块大规模复用的关键挑战，但硬件设计对应物理电路并继承其约束：时序约束（信号在第几周期到达、输入何时被读取）与结构约束（如乘法器多久接受一次新输入）是硬件接口的根本组成部分。现有硬件设计语言无法编码这些约束，用户只能阅读文档、构建脚本甚至模块实现来理解用法。本文提出 Filament——一种面向模块化硬件设计的语言，为静态调度的流水线提供时序与结构约束的规约与强制检查。其核心是时间线类型（timeline types），用于描述给定信号可用或所需的时钟周期区间。Filament 支持硬件模块的安全组合，确保所得设计被正确流水线化，并能可预测地将其降低为高效硬件。
Modular design is a key challenge for enabling large-scale reuse of hardware modules. Unlike software, however, hardware designs correspond to physical circuits and inherit constraints from them. Timing constraints—which cycle a signal arrives, when an input is read—and structural constraints—how often a multiplier accepts new inputs—are fundamental to hardware interfaces. Existing hardware design languages do not provide a way to encode these constraints; a user must read documentation, build scripts, or in the worst case, a module’s implementation to understand how to use it. We present Filament, a language for modular hardware design that supports the specification and enforcement of timing and structural constraints for statically scheduled pipelines. Filament usestimeline types, which describe the intervals of clock-cycle time when a given signal is available or required. Filament enablessafe compositionof hardware modules, ensures that the resulting designs are correctly pipelined, and predictably lowers them to efficient hardware.
@article{paperbot1969,
title = {Modular Hardware Design with Timeline Types},
author = {Rachit Nigam and Pedro Henrique Azevedo de Amorim and Adrian Sampson},
journal = {Proceedings of the ACM on Programming Languages},
volume = {7},
number = {PLDI},
year = {2023},
doi = {10.1145/3591234}
}