一句话：提出硬件反编译问题，并用克隆检测与程序合成技术将网表中的重复逻辑重卷为 HDL 循环。
本文提出“硬件反编译”这一新问题：与软件反编译类似，它旨在分析低层产物——由线与逻辑门构成的网表——以恢复高层编程抽象，并据此生成硬件描述语言（HDL）代码。完整的硬件反编译需要多个环节，本文聚焦其中一环：硬件循环重卷（hardware loop rerolling）。该技术利用克隆检测与程序合成，识别网表中由原始 HDL 循环综合而来的重复逻辑，并将其重卷为恢复出的 HDL 代码中的语法循环结构。作者在 PyRTL HDL 与工业标准 SystemVerilog 编写的硬件设计基准上进行评估：实现能在基准套件的 53 个网表中对 52 个成功识别并重卷循环。文中还给出三个体现实用价值的示例：HDL 之间的转译、相对网表更快的仿真（平均加速 6 倍）以及产物压缩（平均缩小 39%）。
We introduce the new problem of hardware decompilation . Analogous to software decompilation, hardware decompilation is about analyzing a low-level artifact—in this case a netlist , i.e., a graph of wires and logical gates representing a digital circuit—in order to recover higher-level programming abstractions, and using those abstractions to generate code written in a hardware description language (HDL). The overall problem of hardware decompilation requires a number of pieces. In this paper we focus on one specific piece of the puzzle: a technique we call hardware loop rerolling . Hardware loop rerolling leverages clone detection and program synthesis techniques to identify repeated logic in netlists (such as would be synthesized from loops in the original HDL code) and reroll them into syntactic loops in the recovered HDL code. We evaluate hardware loop rerolling for hardware decompilation over a set of hardware design benchmarks written in the PyRTL HDL and industry standard SystemVerilog. Our implementation identifies and rerolls loops in 52 out of 53 of the netlists in our benchmark suite, and we show three examples of how hardware decompilation can provide concrete benefits: transpilation between HDLs, faster simulation times over netlists (with mean speedup of 6x), and artifact compaction (39% smaller on average).
@article{paperbot1975,
title = {Loop Rerolling for Hardware Decompilation},
author = {Zachary D. Sisco and Jonathan Balkind and Timothy Sherwood and Ben Hardekopf},
journal = {Proceedings of the ACM on Programming Languages},
volume = {7},
number = {PLDI},
year = {2023},
doi = {10.1145/3591237}
}