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P2 Modular Control Plane Verification via Temporal Invariants

基于时序不变量的模块化控制平面验证
PLDI 7(PLDI)2023匹配度 4/10 · 论文属于形式化验证/程序验证,采用时序逻辑启发的模块化验证方法,与用户关注的静态分析/形式化验证方向有一定方法论邻近性;但它不涉及 LLM/Agent、浮点程序分析或贝叶斯程序分析,应用域为网络控制平面,并非用户当前研究的核心交叉点。引用 22 inbox
Timothy Alberdingk Thijm, Ryan Beckett, Aarti Gupta, David Walker
crossref: 2026-09-10

AI 速览

一句话:提出 Timepiece,用逻辑时间路由模型与受时序逻辑启发的接口谓词,实现可靠可扩展的模块化控制平面验证。

单体控制平面验证难以扩展到数万节点、异构策略且日变更频繁的网络;模块化验证可提升扩展性,但直接套用稳定路径模型并不可靠。本文提出 Timepiece,采用基于逻辑时间的路由模型,并要求用户用受时序逻辑启发的谓词指定模块接口。基于这些接口,系统构建可靠、表达力强且可扩展的验证引擎,支持可达性、访问控制等全网性质验证,并保留 SMT 符号推理能力。评估中,非模块化引擎验证 80 节点 fattree 的 prefix-filtering 策略 2 小时后超时;Timepiece 在 96 核虚拟机上 2.37 分钟验证 2000 节点 fattree,单路由器模块化验证可并行完成,仅需数秒。

问题
单体控制平面验证无法扩展到超大规模网络,而现有稳定路径模型在模块化验证中并不可靠。
方法
Timepiece 采用基于逻辑时间的路由模型,要求用受时序逻辑启发的谓词定义模块接口,并据此进行基于 SMT 的模块化符号验证。
评估
在 fattree 网络上比较非模块化与模块化验证:非模块化引擎验证 80 节点 2 小时超时,Timepiece 在 96 核虚拟机上 2.37 分钟验证 2000 节点,单路由器验证可并行数秒完成。
原文摘要(Abstract)

Monolithic control plane verification cannot scale to hyperscale network architectures with tens of thousands of nodes, heterogeneous network policies and thousands of network changes a day. Instead, modular verification offers improved scalability, reasoning over diverse behaviors, and robustness following policy updates. We introduce Timepiece, a new modular control plane verification system. While one class of verifiers, starting with Minesweeper, were based on analysis of stable paths, we show that such models, when deployed naïvely for modular verification, are unsound. To rectify the situation, we adopt a routing model based around a logical notion of time and develop a sound, expressive, and scalable verification engine. Our system requires that a user specifies interfaces between module components. We develop methods for defining these interfaces using predicates inspired by temporal logic, and show how to use those interfaces to verify a range of network-wide properties such as reachability or access control. Verifying a prefix-filtering policy using a non-modular verification engine times out on an 80-node fattree network after 2 hours. However, Timepiece verifies a 2,000-node fattree in 2.37 minutes on a 96-core virtual machine. Modular verification of individual routers is embarrassingly parallel and completes in seconds, which allows verification to scale beyond non-modular engines, while still allowing the full power of SMT-based symbolic reasoning.

链接与引用

DOI 原文 · PDF(开放获取) ·

BibTeX
@article{paperbot2006,
  title = {Modular Control Plane Verification via Temporal Invariants},
  author = {Timothy Alberdingk Thijm and Ryan Beckett and Aarti Gupta and David Walker},
  journal = {Proceedings of the ACM on Programming Languages},
  volume = {7},
  number = {PLDI},
  year = {2023},
  doi = {10.1145/3591222}
}