一句话：提出 hazard interfaces 将冒险引发的跨级依赖封装于接口中，实现含各类冒险的流水线电路模块化设计。
流水线电路的模块化设计因结构、数据和控制冒险而困难：停顿、旁路和丢弃重启等冒险消解机制会引入跨级依赖，可能导致单体控制逻辑和组合环。现有 valid-ready 接口仅适用于含结构冒险的简单流水线。本文提出 hazard interfaces，它是 valid-ready 接口的泛化，核心思想是将跨级依赖包裹在接口内部，从而模块化含结构、数据与控制冒险的流水线电路。作者还设计了 map-reduce 风格的组合子以分解控制逻辑，并为支持这些接口与组合子的原型语言实现了到可综合 Verilog 的编译器，以及一个可靠且高效的类型检查器来证明不存在组合环。在 5 级 RISC-V CPU 核和 100 Gbps 以太网 NIC 上的案例研究表明，hazard interfaces 确实促进了模块化设计，且相比 Chisel 和 Verilog 参考设计在性能、功耗和面积上均无明显开销。
Modular design is critical in reducing hardware designer’s cognitive load and development cost. However, it is challenging to modularize high-performance pipelined circuits with structural, data, and control hazards because their resolution—stalling, and bypassing, and discard-and-restarting—introduce cross-stage dependencies. The dependencies could potentially mandate monolithic control logic and create combinational loops, hindering modular design. An effective method to modularize pipelined circuits is valid-ready interfaces, but they apply to a relatively simple form of pipelined circuits only with structural hazards. We propose hazard interfaces, a generalization of valid-ready interfaces that can modularize pipelined circuits not only with structural but also with data and control hazards. The key idea is enveloping the cross-stage dependencies within interfaces. We also design combinators for hazard interfaces in the style of map-reduce that facilitate decomposition of control logic. We implement a compiler (to synthesizable Verilog) for a prototype language supporting hazard interfaces and combinators, and design a sound and efficient type checker that proves the absence of combinational loops. With case studies on 5-stage RISC-V CPU core and 100 Gbps Ethernet NIC, we demonstrate that hazard interfaces indeed facilitate modular design while incurring no noticeable cost in performance, power, and area over reference designs in Chisel and Verilog. CCS Concepts: • Hardware → Hardware description languages and compilation ; • Software and its engineering → Functional languages .
@article{JangRLZK24,
title = {Modular Hardware Design of Pipelined Circuits with Hazards},
author = {Minseong Jang and Jungin Rhee and Woojin Lee and Shuangshuang Zhao and Jeehoon Kang},
journal = {Proceedings of the ACM on Programming Languages},
volume = {8},
number = {PLDI},
year = {2024},
doi = {10.1145/3656378}
}