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P2 Translation-Triggered Prefetching

地址翻译触发的预取
ASPLOS Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems2017匹配度 0/10 · 该论文属于计算机体系结构中的内存预取与页表硬件优化,研究如何利用地址翻译触发 DRAM 行缓冲和片上缓存预取,与用户关注的程序语言/静态分析、AI 与 PL 交叉、浮点程序分析、贝叶斯程序分析等方向均无直接关联。引用 70 inbox
Abhishek Bhattacharjee
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出 TEMPO,利用页表访问触发对目标数据的 DRAM 行缓冲与片上缓存预取,以极低硬件开销提升内存性能。

现代大数据负载中 20-40% 的 DRAM 引用来自页表访问,且页表查找后 98%+ 会继续访问对应数据。本文提出 TEMPO,一种利用操作系统虚拟内存子系统的低开销硬件预取机制:在地址翻译触发页表查找时,预取页表项指向的数据至 DRAM 行缓冲和片上缓存。TEMPO 仅需对内存控制器做微小改动,无需修改 OS 或应用。评估显示其在增加不到 3% 面积的情况下,性能提升 10-30%,能耗降低 1-14%。

问题
现代大数据负载中大量 DRAM 引用用于访问页表,且页表查找后绝大多数会继续访问对应数据,地址翻译造成显著内存开销。
方法
TEMPO 在页表查找触发时预取页表项所指向的数据,利用 DRAM 行缓冲与片上缓存进行预取,仅需对内存控制器做微小改动。
评估
在内存控制器增加不到 3% 面积、无需修改 OS 或应用的前提下,性能提升 10-30%,能耗降低 1-14%。
原文摘要(Abstract)

We propose translation-enabled memory prefetching optimizations or TEMPO, a low-overhead hardware mechanism to boost memory performance by exploiting the operating system's (OS) virtual memory subsystem. We are the first to make the following observations: (1) a substantial fraction (20-40%) of DRAM references in modern big- data workloads are devoted to accessing page tables; and (2) when memory references require page table lookups in DRAM, the vast majority of them (98%+) also look up DRAM for the subsequent data access. TEMPO exploits these observations to enable DRAM row-buffer and on-chip cache prefetching of the data that page tables point to. TEMPO requires trivial changes to the memory controller (under 3% additional area), no OS or application changes, and improves performance by 10-30% and energy by 1-14%.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{Bhattacharjee17,
  title = {Translation-Triggered Prefetching},
  author = {Abhishek Bhattacharjee},
  booktitle = {ASPLOS},
  year = {2017},
  doi = {10.1145/3037697.3037705}
}