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P2 Typed Architectures

Typed Architectures:类型化架构
ASPLOS Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems2017匹配度 1/10 · 论文关注动态脚本语言在ISA/硬件层面的类型信息保留与运行时类型检查加速,属于体系结构与运行时优化,不涉及静态分析、ML/Agentic程序、浮点程序分析、贝叶斯程序分析或LLM与程序分析的交叉。引用 11 inbox
Channoh Kim, Jaehyeok Kim, Sungmin Kim, Dooyoung Kim, Namho Kim, Gitae Na, Young H. Oh, Hyeon Gyu Cho, Jae W. Lee
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出在 ISA 层保留类型信息的 Typed Architectures,用硬件加速动态脚本语言类型检查与多态操作,降低开销并提升性能。

动态脚本语言虽有高生产力,但其灵活动态类型带来指令数、内存和能耗开销,难以部署于 IoT 单板机。本文提出 Typed Architectures,一种在 ISA 层为变量保留高层类型信息的执行基板:硬件隐式计算与检查动态类型,减少软件类型检查;引入 xadd 等多态指令,在流水线运行时绑定到 add/fadd;并硬件支持 tag-value 布局的类型标签抽取与插入。基于 FPGA 上可综合 RISC-V RTL 的评估表明,对 JavaScript 和 Lua 生产级引擎分别取得 11.2% 与 9.9% 几何平均加速,最高 32.6% 与 43.5%;EDP 改善 19.3% 与 16.5%,40nm 下面积开销 1.6%。

问题
动态脚本语言的动态类型系统导致指令数、内存占用和能耗开销,使其难以部署到 IoT 单板计算机等资源受限环境。
方法
提出 Typed Architectures,在 ISA 层保留变量类型信息,用硬件隐式类型检查、多态指令运行时绑定以及类型标签抽取/插入来加速动态脚本语言。
评估
在 FPGA 上以可综合 RISC-V RTL 实现,并用 JavaScript 与 Lua 生产级引擎评估速度、EDP 和面积开销。
原文摘要(Abstract)

Dynamic scripting languages are becoming more and more widely adopted not only for fast prototyping but also for developing production-grade applications. They provide high-productivity programming environments featuring high levels of abstraction with powerful built-in functions, automatic memory management, object-oriented programming paradigm and dynamic typing. However, their flexible, dynamic type systems easily become the source of inefficiency in terms of instruction count, memory footprint, and energy consumption. This overhead makes it challenging to deploy these high-productivity programming technologies on emerging single-board computers for IoT applications. Addressing this challenge, this paper introduces Typed Architectures, a high-efficiency, low-cost execution substrate for dynamic scripting languages, where each data variable retains high-level type information at an ISA level. Typed Architectures calculate and check the dynamic type of each variable implicitly in hardware, rather than explicitly in software, hence significantly reducing instruction count for dynamic type checking. Besides, Typed Architectures introduce polymorphic instructions (e.g., xadd), which are bound to the correct native instruction at runtime within the pipeline (e.g., add or fadd) to efficiently implement polymorphic operators. Finally, Typed Architectures provide hardware support for flexible yet efficient type tag extraction and insertion, capturing common data layout patterns of tag-value pairs. Our evaluation using a fully synthesizable RISC-V RTL design on FPGA shows that Typed Architectures achieve geomean speedups of 11.2% and 9.9% with maximum speedups of 32.6% and 43.5% for two production-grade scripting engines for JavaScript and Lua, respectively. Moreover, Typed Architectures improve the energy-delay product (EDP) by 19.3% for JavaScript and 16.5% for Lua with an area overhead of 1.6% at a 40nm technology node.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{KimKKKKNOCL17,
  title = {Typed Architectures},
  author = {Channoh Kim and Jaehyeok Kim and Sungmin Kim and Dooyoung Kim and Namho Kim and Gitae Na and Young H. Oh and Hyeon Gyu Cho and Jae W. Lee},
  booktitle = {ASPLOS},
  year = {2017},
  doi = {10.1145/3037697.3037726}
}