一句话:提出CTA聚类软件技术,挖掘跨CTA局部性并重排调度,提升GPU缓存性能。
现代GPU的L1数据缓存作用有限:跨SM访存局部性主要由高延迟L2承接,核内局部性依赖scratchpad。论文揭示长期被忽略的inter-CTA局部性。作者在多种现代GPU上实证证明该局部性可在L1或L1/Tex统一缓存上时空复用,并量化其普遍性与显著性。基于此提出CTA-Clustering及软件技术,在不改硬件前提下重排默认CTA调度,将可能复用的CTA聚合到同一SM,并集成自动优化框架。在Fermi、Kepler、Maxwell、Pascal上,L2事务平均减少55%、65%、29%、28%,应用平均加速1.46x、1.48x、1.45x、1.41x,最高约3.8x。
Cache is designed to exploit locality; however, the role of on-chip L1 data caches on modern GPUs is often awkward. The locality among global memory requests from different SMs (Streaming Multiprocessors) is predominantly harvested by the commonly-shared L2 with long access latency; while the in-core locality, which is crucial for performance delivery, is handled explicitly by user-controlled scratchpad memory. In this work, we disclose another type of data locality that has been long ignored but with performance boosting potential --- the inter-CTA locality. Exploiting such locality is rather challenging due to unclear hardware feasibility, unknown and inaccessible underlying CTA scheduler, and small in-core cache capacity. To address these issues, we first conduct a thorough empirical exploration on various modern GPUs and demonstrate that inter-CTA locality can be harvested, both spatially and temporally, on L1 or L1/Tex unified cache. Through further quantification process, we prove the significance and commonality of such locality among GPU applications, and discuss whether such reuse is exploitable. By leveraging these insights, we propose the concept of CTA-Clustering and its associated software-based techniques to reshape the default CTA scheduling in order to group the CTAs with potential reuse together on the same SM. Our techniques require no hardware modification and can be directly deployed on existing GPUs. In addition, we incorporate these techniques into an integrated framework for automatic inter-CTA locality optimization. We evaluate our techniques using a wide range of popular GPU applications on all modern generations of NVIDIA GPU architectures. The results show that our proposed techniques significantly improve cache performance through reducing L2 cache transactions by 55%, 65%, 29%, 28% on average for Fermi, Kepler, Maxwell and Pascal, respectively, leading to an average of 1.46x, 1.48x, 1.45x, 1.41x (up to 3.8x, 3.6x, 3.1x, 3.3x) performance speedups for applications with algorithm-related inter-CTA reuse.