一句话：提出可编程存内处理器架构与数据并行编程/编译框架，将TensorFlow程序映射到存内处理器并取得显著加速。
针对计算型非易失性存储器虽能显著提升性能、却依赖人工将专用内核映射到存储阵列而难以执行通用负载的问题，本文提出可编程存内处理器架构及数据并行编程框架。该架构以紧凑指令集为存储阵列提供通用计算能力，并依靠大规模并行与减少数据搬运提升效率；编程框架融合数据流与向量处理思想以利用底层硬件并行性，同时开发编译框架，将TensorFlow输入生成存内处理器代码。评估表明，在Parsec应用集上较多核CPU服务器取得7.5倍加速，在Rodinia基准上较服务器级GPU取得763倍加速。
Recent developments in Non-Volatile Memories (NVMs) have opened up a new horizon for in-memory computing. Despite the significant performance gain offered by computational NVMs, previous works have relied on manual mapping of specialized kernels to the memory arrays, making it infeasible to execute more general workloads. We combat this problem by proposing a programmable in-memory processor architecture and data-parallel programming framework. The efficiency of the proposed in-memory processor comes from two sources: massive parallelism and reduction in data movement. A compact instruction set provides generalized computation capabilities for the memory array. The proposed programming framework seeks to leverage the underlying parallelism in the hardware by merging the concepts of data-flow and vector processing. To facilitate in-memory programming, we develop a compilation framework that takes a TensorFlow input and generates code for our in-memory processor. Our results demonstrate 7.5x speedup over a multi-core CPU server for a set of applications from Parsec and 763x speedup over a server-class GPU for a set of Rodinia benchmarks.
DOI 原文 ·
@inproceedings{paperbot4244,
title = {In-Memory Data Parallel Processor},
author = {Daichi Fujiki and Scott Mahlke and Reetuparna Das},
booktitle = {ASPLOS},
year = {2018},
doi = {10.1145/3173162.3173171}
}