一句话：提出 Slim NoC，利用度-直径图与非素数有限域实现端口数最少、面积/能耗更优的可扩展片上网络。
面向数百至数千核芯片对片上网络能效、面积效率与可扩展性的需求，论文提出 Slim NoC。其核心是利用图论中的度-直径图与数论中的非素数有限域，在给定核数下最小化网络端口数；同时借鉴先进片外拓扑的优势，设计 NoC 专用布局，并可结合 Elastic Links 等路由微架构。大量实验表明，Slim NoC 在面积、延迟、吞吐以及静态/动态功耗上均优于传统低基数拓扑（mesh、torus）和现代高基数网络（多种 Flattened Butterfly），覆盖合成与真实工作负载。
Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-chip network design that delivers significant improvements in efficiency and scalability compared to the state-of-the-art. The key idea is to use two concepts from graph and number theory, degree-diameter graphs combined with non-prime finite fields, to enable the smallest number of ports for a given core count. SN is inspired by state-of-the-art off-chip topologies; it identifies and distills their advantages for NoC settings while solving several key issues that lead to significant overheads on-chip. SN provides NoC-specific layouts, which further enhance area/energy efficiency. We show how to augment SN with state-of-the-art router microarchitecture schemes such as Elastic Links, to make the network even more scalable and efficient. Our extensive experimental evaluations show that SN outperforms both traditional low-radix topologies (e.g., meshes and tori) and modern high-radix networks (e.g., various Flattened Butterflies) in area, latency, throughput, and static/dynamic power consumption for both synthetic and real workloads. SN provides a promising direction in scalable and energy-efficient NoC topologies.
DOI 原文 ·
@inproceedings{paperbot4300,
title = {Slim NoC},
author = {Maciej Besta and Syed Minhaj Hassan and Sudhakar Yalamanchili and Rachata Ausavarungnirun and Onur Mutlu and Torsten Hoefler},
booktitle = {ASPLOS},
year = {2018},
doi = {10.1145/3173162.3177158}
}