一句话：提出首个 Verilog JIT 编译器 Cascade，先在软件模拟器中立即执行，后台编译后再迁移到硬件。
FPGA 可提供显著加速，但其编译过程极其缓慢，常需数小时甚至更久。论文将软件领域的 JIT 思想引入硬件设计：代码先在软件模拟器中立即执行，编译在后台进行，完成后迁移到硬件，用户感知为程序逐渐变快。作者实现 Cascade，首个面向 Verilog 的 JIT 编译器。它将启动编译到运行代码的等待时间降至一秒以内，并支持对硬件的通用 printf 调试；在调试环境中性能损失控制在 3 倍以内，对最终设计影响很小，且对会操作相连 IO 设备的程序同样成立。用户研究显示，Cascade 促使更频繁编译，并缩短产生可用硬件设计的时间。
FPGAs offer compelling acceleration opportunities for modern applications. However compilation for FPGAs is painfully slow, potentially requiring hours or longer. We approach this problem with a solution from the software domain: the use of a JIT. Code is executed immediately in a software simulator, and compilation is performed in the background. When finished, the code is moved into hardware, and from the user's perspective it simply gets faster. We have embodied these ideas in Cascade: the first JIT compiler for Verilog. Cascade reduces the time between initiating compilation and running code to less than a second, and enables generic printf debugging from hardware. Cascade preserves program performance to within 3× in a debugging environment, and has minimal effect on a finalized design. Crucially, these properties hold even for programs that perform side effects on connected IO devices. A user study demonstrates the value to experts and non-experts alike: Cascade encourages more frequent compilation, and reduces the time to produce working hardware designs.
DOI 原文 ·
@inproceedings{paperbot4850,
title = {Just-In-Time Compilation for Verilog},
author = {Eric Schkufza and Michael Wei and Christopher J. Rossbach},
booktitle = {ASPLOS},
year = {2019},
doi = {10.1145/3297858.3304010}
}