一句话：提出 AcMC² 编译器，将概率模型转换为基于 MCMC 的 FPGA/ASIC 硬件加速器，并通过依赖分析优化并行与数据局部性。
概率模型被广泛用于机器学习，可整合结构先验并量化不确定性，但其推断通常计算昂贵。本文提出 AcMC² 编译器，将概率模型转换为使用马尔可夫链蒙特卡洛（MCMC）从后验分布采样并查询的优化硬件加速器，目标为 FPGA 或 ASIC。编译器分析模型中的统计依赖关系，以此驱动多项优化，最大化利用问题中可用的并行性和数据局部性。作者在 Xilinx Virtex-7 FPGA 上实现多个学习与推断任务：生成加速器相比 6 核 IBM Power8 CPU 取得 47–100× 运行时间提升，相比 NVIDIA K80 GPU 提升 8–18×；每瓦性能分别提升 753–1600× 和 248–463×。
Probabilistic models (PMs) are ubiquitously used across a variety of machine learning applications. They have been shown to successfully integrate structural prior information about data and effectively quantify uncertainty to enable the development of more powerful, interpretable, and efficient learning algorithms. This paper presents AcMC2, a compiler that transforms PMs into optimized hardware accelerators (for use in FPGAs or ASICs) that utilize Markov chain Monte Carlo methods to infer and query a distribution of posterior samples from the model. The compiler analyzes statistical dependencies in the PM to drive several optimizations to maximally exploit the parallelism and data locality available in the problem. We demonstrate the use of AcMC2 to implement several learning and inference tasks on a Xilinx Virtex-7 FPGA. AcMC2-generated accelerators provide a 47-100× improvement in runtime performance over a 6-core IBM Power8 CPU and a 8-18× improvement over an NVIDIA K80 GPU. This corresponds to a 753-1600× improvement over the CPU and 248-463× over the GPU in performance-per-watt terms.