一句话：提出基于忆阻器的可编程加速器 PUMA 及配套编译器，使多种 ML 推理负载在保持可编程性的同时实现高能效。
忆阻器 crossbar 能以模拟方式执行矩阵向量乘法，但此前加速器多为专用设计，仅覆盖有限神经网络应用。本文提出 PUMA：在 crossbar 上加入通用执行单元，通过专用 ISA 暴露微体系结构，兼顾内存计算/模拟电路效率与可编程性。其编译器把高层代码翻译为 PUMA ISA，划分计算图并优化指令调度与寄存器分配，支持数千空间核心上的大规模负载。作者用含功能、时序与功耗模型的模拟器评估。1 GHz PUMA 达到 577 GOPS/s/mm²、837 GOPS/s/W；在图像识别、机器翻译与语言建模（5M–800M 突触）上，相较 GPU 能效最高提升 2,446×、延迟改善 66×；相较专用忆阻器加速器仅增加少量能耗。
Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications. We present the Programmable Ultra-efficient Memristor-based Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability. We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores. We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of 577 GOPS/s/mm 2 and 837~GOPS/s/W, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to 2,446× energy and 66× latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.
DOI 原文 ·
@inproceedings{paperbot4867,
title = {PUMA},
author = {Aayush Ankit and Izzat El Hajj and Sai Rahul Chalamalasetti and Geoffrey Ndu and Martin Foltin and R. Stanley Williams and Paolo Faraboschi and Wen-mei W Hwu and John Paul Strachan and Kaushik Roy and Dejan S. Milojicic},
booktitle = {ASPLOS},
year = {2019},
doi = {10.1145/3297858.3304049}
}