一句话：提出面向分块神经网络加速器的数据流优化，通过缓冲共享与交替层循环顺序提升性能并降低能耗。
随着神经网络规模与复杂度增长，扩展 NN 加速器的能力与效率变得至关重要。分块架构通过层内并行与层间流水线支持粗粒度并行，但现有并行数据流存在数据重复、访存开销大、缓冲需求高和流水线延迟等问题。本文提出面向分块 NN 加速器的数据流优化：针对层内并行，设计缓冲共享数据流，将分布式缓冲虚拟为理想共享缓冲，消除过度数据复制和访存开销；针对层间流水线，提出交替层循环顺序，以更细粒度、更及时的方式转发中间数据，降低缓冲需求和流水线延迟，并使其适用于复杂 DAG 结构的 NN。在广泛 NN 上，优化使分块 NN 加速器性能提升 2 倍、能耗降低 45%，且效果随 NN 规模和复杂度增加而增强。
The use of increasingly larger and more complex neural networks (NNs) makes it critical to scale the capabilities and efficiency of NN accelerators. Tiled architectures provide an intuitive scaling solution that supports both coarse-grained parallelism in NNs: intra-layer parallelism, where all tiles process a single layer, and inter-layer pipelining, where multiple layers execute across tiles in a pipelined manner. This work proposes dataflow optimizations to address the shortcomings of existing parallel dataflow techniques for tiled NN accelerators. For intra-layer parallelism, we develop buffer sharing dataflow that turns the distributed buffers into an idealized shared buffer, eliminating excessive data duplication and the memory access overheads. For inter-layer pipelining, we develop alternate layer loop ordering that forwards the intermediate data in a more fine-grained and timely manner, reducing the buffer requirements and pipeline delays. We also make inter-layer pipelining applicable to NNs with complex DAG structures. These optimizations improve the performance of tiled NN accelerators by 2x and reduce their energy consumption by 45% across a wide range of NNs. The effectiveness of our optimizations also increases with the NN size and complexity.