一句话：提出用扩展竞态逻辑自然编码树分类器，并设计可编程低功耗加速器，验证其在传感器内分类中的能效优势。
针对极低能耗处理场景，数据表示方式会显著影响能效与可实现操作。论文提出利用竞态逻辑（race logic）——以时间编码信号并按数据流方式处理——为传感器内处理提供新能力。作者扩展竞态逻辑操作，使其能自然编码基于树的分类器，并将常见分类任务实现为可编程加速器。为验证假设，他们设计多种集成学习器的竞态逻辑实现，与先进分类器比较，并进行体系结构设计空间探索。原型由 1000 个深度为 6 的可重构竞态树组成，在 14nm CMOS 中达到 15.2M 帧/秒，功耗 613mW。
When extremely low-energy processing is required, the choice of data representation makes a tremendous difference. Each representation (e.g. frequency domain, residue coded, log-scale) comes with a unique set of trade-offs --- some operations are easier in that domain while others are harder. We demonstrate that race logic, in which temporally coded signals are getting processed in a dataflow fashion, provides interesting new capabilities for in-sensor processing applications. Specifically, with an extended set of race logic operations, we show that tree-based classifiers can be naturally encoded, and that common classification tasks can be implemented efficiently as a programmable accelerator in this class of logic. To verify this hypothesis, we design several race logic implementations of ensemble learners, compare them against state-of-the-art classifiers, and conduct an architectural design space exploration. Our proof-of-concept architecture, consisting of 1,000 reconfigurable Race Trees of depth 6, will process 15.2M frames/s, dissipating 613mW in 14nm CMOS.
@inproceedings{paperbot4879,
title = {Boosted Race Trees for Low Energy Classification},
author = {Georgios Tzimpragos and Advait Madhavan and Dilip Vasudevan and Dmitri Strukov and Timothy Sherwood},
booktitle = {ASPLOS},
year = {2019},
doi = {10.1145/3297858.3304036}
}