一句话：提出 SOML 读取操作与配套调度算法，用片内并行弥补 3D NAND SSD 芯片数减少带来的并行度损失。
随着 3D NAND 芯片密度大幅提升，构建同等容量 SSD 所需芯片数减少，SSD 可以更紧凑，但整体吞吐随之下降，阻碍了高密度 3D NAND SSD 的广泛采用。作者分析了 600 个存储工作负载，发现小读操作因芯片级并行度降低而性能显著退化。论文提出的核心问题是：能否通过增强片内并行性，把新式 SSD 因芯片数减少而丧失的片间并行性部分赢回来。为此作者设计了 SOML（Single-Operation-Multiple-Location）读操作，可在一次操作中向不同位置同时发起多个片内小读，从而并行服务多个请求，缓解并行度瓶颈；并给出相应的 SOML 读调度算法以充分利用该能力。基于多种存储工作负载的实验结果表明，采用 SOML 读的 8 芯片 SSD 性能可超过 16 芯片的基线 SSD。
NAND-based solid-state disks (SSDs) are known for their superior random read/write performance due to the high degrees of multi-chip parallelism they exhibit. Currently, as the chip density increases dramatically, fewer 3D NAND chips are needed to build an SSD compared to the previous generation chips. As a result, SSDs can be made more compact. However, this decrease in the number of chips also results in reduced overall throughput, and prevents 3D NAND high density SSDs from being widely-adopted. We analyzed 600 storage workloads, and our analysis revealed that the small read operations suffer significant performance degradation due to reduced chip-level parallelism in newer 3D NAND SSDs. The main question is whether some of the inter-chip parallelism lost in these new SSDs (due to the reduced chip count) can be won back by enhancing intra-chip parallelism. Motivated by this question, we propose a novel SOML (Single-Operation-Multiple-Location) read operation, which can perform several small intra-chip read operations to different locations simultaneously, so that multiple requests can be serviced in parallel, thereby mitigating the parallelism-related bottlenecks. A corresponding SOML read scheduling algorithm is also proposed to fully utilize the SOML read. Our experimental results with various storage workloads indicate that, the SOML read-based SSD with 8 chips can outperform the baseline SSD with 16 chips.