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P2 A Hypervisor for Shared-Memory FPGA Platforms

面向共享内存FPGA平台的Hypervisor
ASPLOS Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems2020匹配度 0/10 · 论文研究FPGA共享内存虚拟化hypervisor,属于体系结构与运行时/内存管理方向,与用户关注的程序分析、LLM/Agent、浮点程序分析及贝叶斯程序分析均无直接关联。引用 62 inbox
Jiacheng Ma, Gefei Zuo, Kevin Loughlin, Xiaohe Cheng, Yanqiang Liu, Abel Mulugeta Eneyew, Zhengwei Qi, Baris Kasikci
crossref: 2026-09-12

AI 速览

一句话:首个共享内存FPGA虚拟化hypervisor,用多路复用器树、页表切片与抢占接口实现空间/时间复用。

云厂商用FPGA作加速器并虚拟化复用,但现有虚拟化多限于主机中心模型,加速器不能发DMA,指针追逐负载开销高;共享内存FPGA允许DMA但缺乏虚拟化支持。方法:提出Optimus,首个可扩展共享内存FPGA虚拟化hypervisor,提供空间/时间复用,实现多路复用器树共享FPGA-CPU互连,以页表切片软硬件协同隔离客户地址空间,提供加速器抢占接口。结果:单FPGA支持八个加速器,十二个基准聚合吞吐提升1.98-7倍。

问题
云厂商希望通过虚拟化在客户间复用FPGA,但现有虚拟化多限于主机中心模型,加速器无法直接发起DMA,导致指针追逐负载开销高;共享内存FPGA虽允许DMA,却缺乏虚拟化支持。
方法
提出Optimus,首个可扩展共享内存FPGA虚拟化hypervisor,提供空间与时间复用,实现多路复用器树共享FPGA-CPU互连,以页表切片软硬件协同隔离客户地址空间,并提供加速器抢占接口。
评估
在单个FPGA上支持八个物理加速器,十二个真实基准的聚合吞吐量提升1.98倍至7倍。
原文摘要(Abstract)

Cloud providers widely deploy FPGAs as application-specific accelerators for customer use. These providers seek to multiplex their FPGAs among customers via virtualization, thereby reducing running costs. Unfortunately, most virtualization support is confined to FPGAs that expose a restrictive, host-centric programming model in which accelerators cannot issue direct memory accesses (DMAs). The host-centric model incurs high runtime overhead for workloads that exhibit pointer chasing. Thus, FPGAs are beginning to support a shared-memory programming model in which accelerators can issue DMAs. However, virtualization support for shared-memory FPGAs is limited. This paper presents Optimus, the first hypervisor that supports scalable shared-memory FPGA virtualization. Optimus offers both spatial multiplexing and temporal multiplexing to provide efficient and flexible sharing of each accelerator on an FPGA. To share the FPGA-CPU interconnect at a high clock frequency, Optimus implements a multiplexer tree. To isolate each guest's address space, Optimus introduces the technique of page table slicing as a hardware-software co-design. To support preemptive temporal multiplexing, Optimus provides an accelerator preemption interface. We show that Optimus supports eight physical accelerators on a single FPGA and improves the aggregate throughput of twelve real-world benchmarks by 1.98x-7x.

链接与引用

DOI 原文 ·

BibTeX
@inproceedings{paperbot5429,
  title = {A Hypervisor for Shared-Memory FPGA Platforms},
  author = {Jiacheng Ma and Gefei Zuo and Kevin Loughlin and Xiaohe Cheng and Yanqiang Liu and Abel Mulugeta Eneyew and Zhengwei Qi and Baris Kasikci},
  booktitle = {ASPLOS},
  year = {2020},
  doi = {10.1145/3373376.3378482}
}