一句话：提出 Fleet，用户只需编写串行处理单元的 RTL，框架自动复制并生成大规模并行流式 FPGA 设计。
FPGA 加速通常需要开发者手动编写并行 RTL，门槛高且开发效率低。本文提出 Fleet，一种面向 FPGA 的大规模并行流式模型：用户只需为一个串行处理每个输入 token 的处理单元编写 RTL，这比编写并行处理单元简单得多。Fleet 将该单元自动复制多份，并生成内存控制器，为各单元提供独立输入流并回收输出。Fleet 还提供了基于 Chisel 的处理单元语言，在保留 Chisel 底层性能控制能力的同时，加入自动处理 ready-valid 握手信号以及原生且自动流水化的 BRAM 类型等生产力特性。作者在 JSON 解析、整数压缩等六个应用上评估 Fleet，在 Amazon F1 FPGA 上可容纳数百个处理单元，每瓦性能超过 CPU 实现 400 倍、超过 GPU 实现 9 倍，而代码行数相近。
We present Fleet, a framework that offers a massively parallel streaming model for FPGAs and is effective in a number of domains well-suited for FPGA acceleration, including parsing, compression, and machine learning. Fleet requires the user to specify RTL for a processing unit that serially processes every input token in a stream, a far simpler task than writing a parallel processing unit. It then takes the user's processing unit and generates a hardware design with many copies of the unit as well as memory controllers to feed the units with separate streams and drain their outputs. Fleet includes a Chisel-based processing unit language. The language maintains Chisel's low-level performance control while adding a few productivity features, including automatic handling of ready-valid signaling and a native and automatically pipelined BRAM type. We evaluate Fleet on six different applications, including JSON parsing and integer compression, fitting hundreds of Fleet processing units on the Amazon F1 FPGA and outperforming CPU implementations by over 400x and GPU implementations by over 9x in performance per watt while requiring a similar number of lines of code.