一句话：利用有界自动机学习将遗留字符串内核高效映射到 FPGA 等加速器，减少低层重写和手工架构优化。
硬件加速器（如 FPGA）在通用计算流水线中日益普及，但其编程模型远落后于 CPU：遗留程序常需在极低抽象层次重写，并要求开发者熟悉目标加速器架构。高层综合虽能帮助移植部分遗留软件，但许多程序若缺乏手工、架构相关的优化则性能不佳。本文聚焦遗留字符串内核，提出通过有界自动机学习来加速这类内核，目标是以自动机学习驱动的转换替代或减少底层重写与手工架构优化。给出的摘要未报告具体评估结果与性能提升幅度。
The adoption of hardware accelerators, such as FPGAs, into general-purpose computation pipelines continues to rise, but programming models for these devices lag far behind their CPU counterparts. Legacy programs must often be rewritten at very low levels of abstraction, requiring intimate knowledge of the target accelerator architecture. While techniques such as high-level synthesis can help port some legacy software, many programs perform poorly without manual, architecture-specific optimization.