一句话：用 Halide 调度语言统一表示 DNN 加速器微架构与映射，并优化硬件资源分配以降低能耗。
该工作将 DNN 加速器的微架构与程序映射统一视为七层嵌套循环的循环顺序与硬件并行度选择，为稠密 DNN 加速器建立形式化分类。作者发现这些硬件变体可由 Halide 调度语言精确简洁地表达，并通过修改 Halide 编译器生成硬件，构建能公平比较已有加速器的系统。评估显示，恰当循环分块且硬件支持复制循环映射时，多种数据流能获得相近能效；资源分配尤其是存储系统对能耗与性能影响显著。在保持吞吐不变下优化资源分配，CNN 能耗最多改善 4.2 倍，LSTM 和 MLP 分别改善 1.6 倍和 1.8 倍。
We show that DNN accelerator micro-architectures and their program mappings represent specific choices of loop order and hardware parallelism for computing the seven nested loops of DNNs, which enables us to create a formal taxonomy of all existing dense DNN accelerators. Surprisingly, the loop transformations needed to create these hardware variants can be precisely and concisely represented by Halide's scheduling language. By modifying the Halide compiler to generate hardware, we create a system that can fairly compare these prior accelerators. As long as proper loop blocking schemes are used, and the hardware can support mapping replicated loops, many different hardware dataflows yield similar energy efficiency with good performance. This is because the loop blocking can ensure that most data references stay on-chip with good locality and the processing units have high resource utilization. How resources are allocated, especially in the memory system, has a large impact on energy and performance. By optimizing hardware resource allocation while keeping throughput constant, we achieve up to 4.2X energy improvement for Convolutional Neural Networks (CNNs), 1.6X and 1.8X improvement for Long Short-Term Memories (LSTMs) and multi-layer perceptrons (MLPs), respectively.
DOI 原文 ·
@inproceedings{paperbot5479,
title = {Interstellar},
author = {Xuan Yang and Mingyu Gao and Qiaoyi Liu and Jeff Setter and Jing Pu and Ankita Nayak and Steven Bell and Kaidi Cao and Heonjae Ha and Priyanka Raina and Christos Kozyrakis and Mark Horowitz},
booktitle = {ASPLOS},
year = {2020},
doi = {10.1145/3373376.3378514}
}