一句话：提出 DiAG，将寄存器堆抽象为寄存器 lane，在硬件中隐式构建数据流图，以加速器式微架构提升通用处理器的能效。
随着 Dennard 缩放终结与摩尔定律放缓，专用加速器大量涌现，而通用处理器虽易编程且使用广泛，其微架构改进却长期缓慢。本文以加速器式思路重新思考 CPU 微架构，提出 DiAG：一种基于数据流的通用处理器架构，可通过开发指令级并行来最小化延迟，或通过数据级并行来最大化吞吐。DiAG 的核心抽象是将寄存器堆视为寄存器 lane，从而在硬件中隐式构建程序的数据流图；它无需专门的语言、库或编译器，即可支持任意类 RISC 指令集。相比传统乱序微架构，DiAG 以面积增加为代价，带来减少前端开销、高效指令复用和线程级流水线三项收益。作者用 SystemVerilog 实现了支持 RISC-V ISA 的原型，并用 EDA 工具评估性能、功耗与面积；在 Rodinia 与 SPEC CPU2017 基准上，512 个 PE 的 DiAG 配置相对激进乱序 CPU 基线取得 1.18 倍加速和 1.63 倍能效提升。
The end of Dennard scaling and decline of Moore's law has prompted the proliferation of hardware accelerators for a wide range of application domains. Yet, at the dawn of an era of specialized computing, left behind the trend is the general-purpose processor that is still most easily programmed and widely used but has seen incremental changes for decades. This work uses an accelerator-inspired approach to rethink CPU microarchitecture to improve its energy efficiency while retaining its generality. We propose DiAG, a dataflow-based general-purpose processor architecture that can minimize latency by exploiting instruction-level parallelism or maximize throughput by exploiting data-level parallelism. DiAG is designed to support any RISC-like instruction set without explicitly requiring specialized languages, libraries, or compilers. Central to this architecture is the abstraction of the register file as register 'lanes' that allow implicit construction of the program's dataflow graph in hardware. At the cost of increased area, DiAG offers three main benefits over conventional out-of-order microarchitectures: reduced front-end overhead, efficient instruction reuse, and thread-level pipelining. We implement a DiAG prototype that supports the RISC-V ISA in SystemVerilog and evaluate its performance, power consumption, and area with EDA tools. In the tested Rodinia and SPEC CPU2017 benchmarks, DiAG configured with 512 PEs achieves a 1.18x speedup and 1.63x improvement in energy efficiency against an aggressive out-of-order CPU baseline.
DOI 原文 ·
@inproceedings{paperbot6084,
title = {DiAG: a dataflow-inspired architecture for general-purpose processors},
author = {Dong Kai Wang and Nam Sung Kim},
booktitle = {ASPLOS},
year = {2021},
doi = {10.1145/3445814.3446703}
}