一句话：利用 CACHE READ 命令流水化重试步骤并自适应缩短芯片级读延迟，显著降低 SSD 的读重试延迟。
采用先进多级单元（MLC）技术的 3D NAND 闪存虽提供高存储密度，但因大量读重试操作而出现明显性能退化。读重试是保证现代 NAND 闪存可靠性的必要机制，却需要以调整后的读参考电压多次重读目标页，从而大幅增加 SSD 读延迟。作者通过细致分析读机制并对 160 颗真实 3D NAND 闪存芯片进行严格刻画，发现两个可利用的机会：一是 CACHE READ 命令可让闪存芯片以流水线方式执行连续读，二是最终重试步骤中存在较大的 ECC 能力余量。基于此提出两种技术：PR²（Pipelined Read-Retry）用 CACHE READ 流水化相邻重试步骤以缩短整体重试延迟；AR²（Adaptive Read-Retry）根据决定 ECC 余量的当前工作条件动态降低芯片级读延迟，从而缩短每一步重试的耗时。在 12 个真实负载上的评估表明，该方案相对当前最优基线最多将 SSD 响应时间改善 31.5%（平均 17%），且只需对 SSD 控制器做少量修改。
3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-retry operations. Although the read-retry mechanism is essential to ensuring the reliability of modern NAND flash memory, it can significantly in-crease the read latency of an SSD by introducing multiple retry steps that read the target page again with adjusted read-reference voltage values. Through a detailed analysis of the read mechanism and rigorous characterization of 160 real 3D NAND flash memory chips, we find new opportunities to reduce the read-retry latency by exploiting two advanced features widely adopted in modern NAND flash-based SSDs: 1) the CACHE READ command and 2) strong ECC engine. First, we can reduce the read-retry latency using the advanced CACHE READ command that allows a NAND flash chip to perform consecutive reads in a pipelined manner. Second, there exists a large ECC-capability margin in the final retry step that can be used for reducing the chip-level read latency. Based on our new findings, we develop two new techniques that effectively reduce the read-retry latency: 1) Pipelined Read-Retry (PR²) and 2) Adaptive Read-Retry (AR²). PR² reduces the latency of a read-retry operation by pipelining consecutive retry steps using the CACHE READ command. AR² shortens the latency of each retry step by dynamically reducing the chip-level read latency depending on the current operating conditions that determine the ECC-capability margin. Our evaluation using twelve real-world workloads shows that our proposal improves SSD response time by up to 31.5% (17% on average)over a state-of-the-art baseline with only small changes to the SSD controller.
@inproceedings{paperbot6127,
title = {Reducing solid-state drive read latency by optimizing read-retry},
author = {Jisung Park and Myungsuk Kim and Myoungjun Chun and Lois Orosa and Jihong Kim and Onur Mutlu},
booktitle = {ASPLOS},
year = {2021},
doi = {10.1145/3445814.3446719}
}