一句话：提出BayesPerf，用贝叶斯模型联合推断硬件性能计数器读数并设计低延迟加速器，将复用事件下平均误差从40.1%降至7.6%。
硬件性能计数器（HPC）用于提供系统底层架构与微架构事件的动态信息，但其读数易受非确定性影响，例如事件复用导致计数不足或操作系统中断处理行为引入误差。本文提出 BayesPerf，利用领域驱动的贝叶斯模型刻画多个 HPC 之间的微架构关系，并将其读数联合推断为概率分布，从而量化测量不确定性。作者面向 x86 与 ppc64 CPU 设计并实现了一个低延迟、低功耗的模型推理加速器。当事件复用时，BayesPerf 将 HPC 测量的平均误差从 40.1% 降至 7.6%；文中还以 PCIe 传输调度为例说明其在实时决策中的价值。
Hardware performance counters (HPCs) that measure low-level architectural and microarchitectural events provide dynamic contextual information about the state of the system. However, HPC measurements are error-prone due to non determinism (e.g., undercounting due to event multiplexing, or OS interrupt-handling behaviors). In this paper, we present BayesPerf, a system for quantifying uncertainty in HPC measurements by using a domain-driven Bayesian model that captures microarchitectural relationships between HPCs to jointly infer their values as probability distributions. We provide the design and implementation of an accelerator that allows for low-latency and low-power inference of the BayesPerf model for x86 and ppc64 CPUs. BayesPerf reduces the average error in HPC measurements from 40.1% to 7.6% when events are being multiplexed. The value of BayesPerf in real-time decision-making is illustrated with a simple example of scheduling of PCIe transfers.
@inproceedings{paperbot6132,
title = {BayesPerf: minimizing performance monitoring errors using Bayesian statistics},
author = {Subho S. Banerjee and Saurabh Jha and Zbigniew Kalbarczyk and Ravishankar K. Iyer},
booktitle = {ASPLOS},
year = {2021},
doi = {10.1145/3445814.3446739}
}