一句话：提出 Synergy，通过 Verilog 编译变换和运行时支持在现有 FPGA 上实现挂起/恢复、迁移与多路复用。
现代数据中心需要在虚拟化基础设施上按需使用 FPGA，但制造商的硬件虚拟化方案难以提供通用支持。本文提出编译器/运行时协同的 FPGA 虚拟化方案 Synergy：对 Verilog 程序进行编译变换，使生成的硬件能够在符合原程序语义的前提下，以低于时钟周期的粒度将控制权交还给软件。基于该能力，Synergy 可在现有 FPGA 上高效支持核心虚拟化原语，包括挂起/恢复、程序迁移以及空间/时间复用。作者在 Altera SoC 集群和 Amazon F1 的 Xilinx FPGA 上虚拟化多种未修改的 FPGA 工作负载；结果显示性能为未虚拟化版本的 3–4 倍以内，且 FPGA 资源占用仅小幅增加。
FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in data centers. Applications in data centers run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider’s business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software at sub-clock-tick granularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is available today. We use Synergy to virtualize FPGA workloads across a cluster of Altera SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3−4× of unvirtualized performance, and incur a modest increase in FPGA fabric utilization.