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P2 SIMDRAM: a framework for bit-serial SIMD processing using DRAM

SIMDRAM:一种使用 DRAM 的位串行 SIMD 处理框架
ASPLOS Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems2021匹配度 1/10 · 该论文属于DRAM内计算与位串行SIMD体系结构方向,核心是硬件/ISA支持,与用户关注的程序分析、LLM/Agent、浮点程序分析和贝叶斯程序分析均无直接交集。引用 6 inbox
Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, João Dinis Ferreira, Nika Mansouri Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gómez-Luna, Onur Mutlu
crossref: 2026-09-12

AI 速览

一句话:提出 SIMDRAM 框架,通过 MAJ/NOT 表示和 DRAM 命令序列,在 DRAM 中高效实现复杂及用户自定义的位串行 SIMD 操作。

Processing-using-DRAM 此前仅支持逻辑运算、加法等有限基本操作,为实现其广泛应用,必须支持更复杂的操作。本文提出 SIMDRAM,一个灵活通用的 processing-using-DRAM 框架,旨在高效实现复杂操作并支持任意用户自定义操作。框架包含三个关键步骤:首先为给定操作构建高效的 MAJ/NOT 表示;其次分配用于计算的 DRAM 行给输入输出操作数,并生成在 DRAM 中执行该 MAJ/NOT 实现所需的 DRAM 命令序列;最后利用内存控制器内的 SIMDRAM 控制单元管理操作的完整计算过程。论文设计了相应的硬件与 ISA 支持,以解决关键系统集成挑战,并允许程序员无需硬件改动即可使用新的 SIMDRAM 操作。摘要未提供具体评估结果。

问题
processing-using-DRAM 目前仅支持逻辑运算、加法等有限基本操作,缺乏对复杂操作的支持,阻碍了其被广泛采用。
方法
提出 SIMDRAM 框架,分为三步:为操作构建高效的 MAJ/NOT 表示;分配 DRAM 行并生成 DRAM 命令序列;由内存控制器中的 SIMDRAM 控制单元管理执行。同时设计硬件与 ISA 支持,使程序员无需硬件改动即可使用新操作。
评估
摘要未提及具体评估结果;论文通过设计硬件与 ISA 支持来应对系统集成挑战并支持可编程性。
原文摘要(Abstract)

Processing-using-DRAM has been proposed for a limited set of basic operations (i.e., logic operations, addition). However, in order to enable full adoption of processing-using-DRAM, it is necessary to provide support for more complex operations. In this paper, we propose SIMDRAM, a flexible general-purpose processing-using-DRAM framework that (1) enables the efficient implementation of complex operations, and (2) provides a flexible mechanism tosupport the implementation of arbitrary user-defined operations. The SIMDRAM framework comprises three key steps. The first step builds an efficient MAJ/NOT representation of a given desired operation. The second step allocates DRAM rows that are reserved for computation to the operation’s input and output operands, and generates the required sequence of DRAM commands to perform the MAJ/NOT implementation of the desired operation in DRAM. The third step uses the SIMDRAM control unit located inside the memory controller to manage the computation of the operation from start to end, by executing the DRAM commands generated in the second step of the framework. We design the hardware and ISA support for SIMDRAM framework to (1) address key system integration challenges, and (2) allow programmers to employ new SIMDRAM operations without hardware changes.

链接与引用

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BibTeX
@inproceedings{paperbot6155,
  title = {SIMDRAM: a framework for bit-serial SIMD processing using DRAM},
  author = {Nastaran Hajinazar and Geraldo F. Oliveira and Sven Gregorio and João Dinis Ferreira and Nika Mansouri Ghiasi and Minesh Patel and Mohammed Alser and Saugata Ghose and Juan Gómez-Luna and Onur Mutlu},
  booktitle = {ASPLOS},
  year = {2021},
  doi = {10.1145/3445814.3446749}
}