一句话：提出基于 AST 的 Verilog 解析、语义增强数据集构建与编译器引导修复框架，修复 15.24% 缺陷代码并发布 31.8 万样本 RTL 基准。
随着集成电路设计复杂度上升，Verilog 开发的自动化方法愈发重要，但大语言模型受限于领域特定语义约束与高质量训练数据匮乏。本文提出一个基于 AST 的框架，统一完成 Verilog 解析、数据集构建与自动修复：通过静态分析驱动的双阶段语义增强丰富 AST 表示，据此进行结构化数据集构建，并借助编译器引导完成缺陷代码修复。实验表明，该方法修复了 15.24% 的缺陷 Verilog 代码，构建出包含 318,021 个样本的高质量 RTL 基准数据集，并在多个基准上提升了性能。
With the growing complexity of integrated circuit designs, automated methods for Verilog development have become increasingly important. However, large language models remain limited by domain-specific semantic constraints and the lack of high-quality training data. Therefore, this paper proposes an AST-based framework for Verilog parsing, dataset construction, and automatic repair. Static-analysis-driven semantic enhancement is applied to enrich AST representations, which are then used for structured dataset construction and compiler-guided repair. The proposed method repairs 15.24% of defective Verilog code, producing a high-quality RTL benchmark dataset with 318,021 samples and improving performance on multiple benchmarks.
@inproceedings{paperbot9837,
title = {VerilogASTBench: Benchmark Construction of Verilog AST Dataset with Dual-Stage AST Semantic Enhancement Framework},
author = {Luping Zhang and Chao Chen and Dapeng Yan and Hui Xu and Mingsheng Cao and Jingkuan Song and Zhikuang Cai and Yufeng Guo},
booktitle = {FSE},
year = {2026},
doi = {10.1145/3803437.3807383}
}