一句话：提出波流水线一元SFQ架构，融合脉冲流与Race Logic编码，使运算/存储单元JJ数最多降200倍，缓解超导加速器面积约束。
超导计算受严格面积约束和CMOS电压编码遗留架构限制，难以扩展；同时其ps级SFQ脉冲适合脉冲流表示。本文提出波流水线一元SFQ（U-SFQ）架构，融合脉冲流与Race Logic两种编码，并设计乘法器、加法器、存储单元等新型构件，以利用SFQ脉冲自然特性降低面积。作者仿真了三种硬件加速器：空间架构处理单元（PE）、神经网络/DSP点积单元（DPU）和有限脉冲响应（FIR）滤波器。结果显示，相比SFQ二值实现，U-SFQ构件最多减少200倍约瑟夫森结（JJ），呈现面积-延迟权衡，缓解超导技术面积约束。
Superconducting technology is a prime candidate for the future of computing. However, current superconducting prototypes are limited to small-scale examples due to stringent area constraints and complex architectures inspired from voltage-level encoding in CMOS; this is at odds with the ps-wide Single Quantum Flux (SFQ) pulses used in superconductors to carry information. In this work, we propose a wave-pipelined Unary SFQ (U-SFQ) architecture that leverages the advantages of two data representations: pulse-streams and Race Logic (RL). We introduce novel building blocks such as multipliers, adders, and memory cells, which leverage the natural properties of SFQ pulses to mitigate area constraints. We then design and simulate three popular hardware accelerators: i) a Processing Element (PE), typically used in spatial architectures; ii) A dot-product-unit (DPU), one of the most popular accelerators in artificial neural networks and digital signal processing (DSP); and iii) A Finite Impulse Response (FIR) filter, a popular and computationally demanding DSP accelerator. The proposed U-SFQ building blocks require up to 200× fewer JJs compared to their SFQ binary counterparts, exposing an area-delay trade-off. This work mitigates the stringent area constraints of superconducting technology.
@inproceedings{Gonzalez-Guerrero22,
title = {Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators},
author = {Patricia Gonzalez-Guerrero and Meriam Gay Bautista and Darren Lyles and George Michelogiannakis},
booktitle = {ASPLOS},
year = {2022},
doi = {10.1145/3503222.3507765}
}