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P2 SparseCore: stream ISA and processor specialization for sparse computation

SparseCore:面向稀疏计算的流式 ISA 与处理器专用化
ASPLOS Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems2022匹配度 1/10 · 论文属于计算机体系结构/ISA 设计,目标是稀疏张量与图计算的硬件加速,与用户关注的静态分析、LLM/Agent、浮点程序分析、贝叶斯程序分析均无直接关联;仅在“语言与体系结构”大方向上有极弱交集。引用 24 inbox
Gengyu Rao, Jingji Chen, Jason Yik, Xuehai Qian
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出首个通用稀疏计算处理器扩展,以流式 ISA 将流/稀疏向量作为一等公民,灵活加速稀疏张量与图模式计算。

稀疏数据计算日益重要,但现有稀疏加速器多针对特定算法或应用,难以适应快速演进的算法和软件优化。本文提出 SparseCore,这是一种面向稀疏计算的通用处理器扩展。作者扩展指令集架构(ISA),将流或稀疏向量提升为一等公民,并设计高效体系结构组件支持该流式 ISA;新 ISA 直接在流上操作,兼顾高效数据移动与计算。模拟结果表明,SparseCore 在稀疏张量计算和图模式计算上取得显著加速。

问题
现有稀疏计算加速器多为特定算法或应用定制,缺乏灵活性,难以支持复杂代码模式与快速演进的算法。
方法
扩展 ISA 使 stream 或稀疏向量成为一等公民,并设计高效体系结构组件支持流式 ISA,以统一数据移动和计算。
评估
通过模拟评估,在稀疏张量计算和图模式计算上展示出显著加速。
原文摘要(Abstract)

Computation on sparse data is becoming increasingly important for many applications. Recent sparse computation accelerators are designed for specific algorithm/application, making them inflexible with software optimizations. This paper proposes SparseCore, the first general-purpose processor extension for sparse computation that can flexibly accelerate complex code patterns and fast-evolving algorithms. We extend the instruction set architecture (ISA) to make stream or sparse vector first-class citizens, and develop efficient architectural components to support the stream ISA. The novel ISA extension intrinsically operates on streams, realizing both efficient data movement and computation. The simulation results show that SparseCore achieves significant speedups for sparse tensor computation and graph pattern computation.

链接与引用

DOI 原文 · PDF(开放获取) · DBLP

BibTeX
@inproceedings{RaoCYQ22,
  title = {SparseCore: stream ISA and processor specialization for sparse computation},
  author = {Gengyu Rao and Jingji Chen and Jason Yik and Xuehai Qian},
  booktitle = {ASPLOS},
  year = {2022},
  doi = {10.1145/3503222.3507705}
}