一句话：M³v 为每个通用核添加本地多路复用器并虚拟化跨片通信硬件，使分片间的快速路径通信无需 OS 片介入。
M³ 提出一种软硬件协同设计的分片架构，将通用核与专用加速器分片分配给应用，实现统一使用；M³x 通过牺牲部分隔离性支持分片在应用间粗粒度复用，但当归属不同应用的源片向目标片发消息时需经特殊 OS 片走慢路径转发。本文提出 M³v，进一步牺牲应用间部分隔离性以支持不依赖 OS 片的快速路径通信，从而对通用核实现高效的分片复用。其核心手段是：1）为每个通用核增加本地多路复用器；2）虚拟化核中负责跨片通信的硬件组件。作者在 FPGA 平台的 RISC-V 核上构建原型，实验表明 M³v 显著优于 M³x，并可达到与 Linux 相竞争的性能。
The M³ system (ASPLOS ’16) proposed a hardware/software co-design that simplifies integration between general-purpose cores and special-purpose accelerators, allowing users to easily utilize them in a unified manner. M³ is a tiled architecture, whose tiles (cores and accelerators) are partitioned between applications, such that each tile is dedicated to its own application. The M³x system (ATC ’19) extended M³ by trading off some isolation to enable coarse-grained multiplexing of tiles among multiple applications. With M³x, if source tile t₁ runs code of application p and sends a message m to destination tile t₂ while t₂ is currently not associated with p, then m is forwarded to the right place through a “slow path”, via some special OS tile. In this paper, we present M³v, which extends M³x by further trading off some isolation between applications to support “fast path” communication that does not require the said OS tile’s involvement. Thus, with M³v, a tile can be efficiently multiplexed between applications provided it is a general-purpose core. M³v achieves this goal by 1) adding a local multiplexer to each such core, and by 2) virtualizing the core’s hardware component responsible for cross-tile communications. We prototype M³v using RISC-V cores on an FPGA platform and show that it significantly outperforms M³x and may achieve competitive performance to Linux.
@inproceedings{AsmussenHWMR22,
title = {Efficient and scalable core multiplexing with M³v},
author = {Nils Asmussen and Sebastian Haas and Carsten Weinhold and Till Miemietz and Michael Roitzsch},
booktitle = {ASPLOS},
year = {2022},
doi = {10.1145/3503222.3507741}
}