一句话：提出基于 RISC-V 的 BiSon-e 加速器，用二进制分段与标量 FU 上的 SIMD 加速边缘窄整数线性代数。
字节与子字节整数的线性代数核心广泛用于深度学习与模式匹配，但迁移到资源受限的边缘设备时，其高计算强度成为挑战。本文提出基于 RISC-V 的轻量级加速器 BiSon-e：利用二进制分段降低窄整数核心的内存占用与算术强度，并在现成标量功能单元上执行 SIMD 操作。作者将其集成到完整 RISC-V SoC，在 65nm 和 22nm 工艺下实现仅 0.07% 的面积开销。实验表明，对 AlexNet 与 VGG-16 的卷积和全连接层进行 8/4/2 比特计算，执行时间相比单核标量 RISC-V 最高提升 5.6×、13.9×、24×；字符串匹配能效相比 RISC-V VPU 提升 5×。
Linear algebra computational kernels based on byte and sub-byte integer data formats are at the base of many classes of applications, ranging from Deep Learning to Pattern Matching. Porting the computation of these applications from cloud to edge and mobile devices would enable significant improvements in terms of security, safety, and energy efficiency. However, despite their low memory and energy demands, their intrinsically high computational intensity makes the execution of these workloads challenging on highly resource-constrained devices. In this paper, we present BiSon-e, a novel RISC-V based architecture that accelerates linear algebra kernels based on narrow integer computations on edge processors by performing Single Instruction Multiple Data (SIMD) operations on off-the-shelf scalar Functional Units (FUs). Our novel architecture is built upon the binary segmentation technique, which allows to significantly reduce the memory footprint and the arithmetic intensity of linear algebra kernels requiring narrow data sizes. We integrate BiSon-e into a complete System-on-Chip (SoC) based on RISC-V, synthesized and Place&Routed in 65nm and 22nm technologies, introducing a negligible 0.07% area overhead with respect to the baseline architecture. Our experimental evaluation shows that, when computing the Convolution and Fully-Connected layers of the AlexNet and VGG-16 Convolutional Neural Networks (CNNs) with 8-, 4-, and 2-bit, our solution gains up to 5.6×, 13.9× and 24× in execution time compared to the scalar implementation of a single RISC-V core, and improves the energy efficiency of string matching tasks by 5× when compared to a RISC-V-based Vector Processing Unit (VPU).
@inproceedings{ReggianiLBCOU22,
title = {BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge},
author = {Enrico Reggiani and Cristóbal Ramírez Lazo and Roger Figueras Bagué and Adrián Cristal and Mauro Olivieri and Osman Sabri Unsal},
booktitle = {ASPLOS},
year = {2022},
doi = {10.1145/3503222.3507746}
}