一句话：通过页表扁平化和页表项缓存优先，将页表遍历降至单次访问并显著提升虚拟化性能。
大内存应用因 TLB 覆盖不足而频繁页表遍历，付出多次访问与延迟。本文提出两种互补技术：将传统 4KB 页表两级节点合并为单个 2MB 节点以扁平化页表，降低遍历深度和间接次数；并在高 TLB 缺失期偏置缓存替换以保留页表项。评估覆盖原生与虚拟化系统、内存碎片场景及服务器/移动系统，且内核与硬件改动小。扁平化将遍历访问降至 1.0 次，但因已有 Page Walker Cache（1.5 次）仅提升 2.3%；缓存优先提升 6.8%，结合提升 9.2%。虚拟化下扁平化将遍历从 4.4 降至 2.8 次，提升 7.1%，结合后性能提升 14.0%，动态缓存能耗降低 8.7%，动态 DRAM 能耗降低 4.7%。
As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically "flattening" the page table: merging two levels of traditional 4 KB page table nodes into a single 2 MB node, thereby reducing the table's depth and the number of indirections required to traverse it. The second is accomplished by biasing the cache replacement algorithm to keep page table entries during periods of high TLB miss rates, as these periods also see high data miss rates and are therefore more likely to benefit from having the smaller page table in the cache than to suffer from increased data cache misses. We evaluate these approaches for both native and virtualized systems and across a range of realistic memory fragmentation scenarios, describe the limited changes needed in our kernel implementation and hardware design, identify and address challenges related to self-referencing page tables and kernel memory allocation, and compare results across server and mobile systems using both academic and industrial simulators for robustness. We find that flattening does reduce the number of accesses required on a page walk (to 1.0), but its performance impact (+2.3%) is small due to Page Walker Caches (already 1.5 accesses). Prioritizing caching has a larger effect (+6.8%), and the combination improves performance by +9.2%. Flattening is more effective on virtualized systems (4.4 to 2.8 accesses, +7.1% performance), due to 2D page walks. By combining the two techniques we demonstrate a state-of-the-art +14.0% performance gain and -8.7% dynamic cache energy and -4.7% dynamic DRAM energy for virtualized execution with very simple hardware and software changes.
@inproceedings{0001VSB22,
title = {Every walk’s a hit: making page walks single-access cache hits},
author = {Chang Hyun Park and Ilias Vougioukas and Andreas Sandberg and David Black-Schaffer},
booktitle = {ASPLOS},
year = {2022},
doi = {10.1145/3503222.3507718}
}