一句话：提出 Taurus 数据平面架构，用可编程网络设备上的并行 MapReduce 硬件实现线速逐包机器学习推断。
现代数据中心网络需要在数据平面以线速执行逐包决策，而现有控制平面延迟高，难以满足应用 SLO。Taurus 为可编程交换机和 NIC 增加定制硬件，基于 MapReduce 抽象和流水线 SIMD 并行，支持逐包 MapReduce 操作与 ML 推断。评估显示 Taurus 交换机 ASIC 运行真实模型时比基于服务器的控制平面快数个数量级，面积仅增加 3.8%，线速 ML 模型延迟最多增加 221 ns；FPGA 原型达到完整模型精度，并比最先进控制平面异常检测系统多检测两个数量级的事件。
Emerging applications---cloud computing, the internet of things, and augmented/virtual reality---demand responsive, secure, and scalable datacenter networks. These networks currently implement simple, per-packet, data-plane heuristics (e.g., ECMP and sketches) under a slow, millisecond-latency control plane that runs data-driven performance and security policies. However, to meet applications' service-level objectives (SLOs) in a modern data center, networks must bridge the gap between line-rate, per-packet execution and complex decision making. In this work, we present the design and implementation of Taurus, a data plane for line-rate inference. Taurus adds custom hardware based on a flexible, parallel-patterns (MapReduce) abstraction to programmable network devices, such as switches and NICs; this new hardware uses pipelined SIMD parallelism to enable per-packet MapReduce operations (e.g., inference). Our evaluation of a Taurus switch ASIC---supporting several real-world models---shows that Taurus operates orders of magnitude faster than a server-based control plane while increasing area by 3.8% and latency for line-rate ML models by up to 221 ns. Furthermore, our Taurus FPGA prototype achieves full model accuracy and detects two orders of magnitude more events than a state-of-the-art control-plane anomaly-detection system.
DOI 原文 · arXiv · PDF（开放获取） · DBLP
@inproceedings{SwamyR0GO22,
title = {Taurus: a data plane architecture for per-packet ML},
author = {Tushar Swamy and Alexander Rucker and Muhammad Shahbaz and Ishan Gaur and Kunle Olukotun},
booktitle = {ASPLOS},
year = {2022},
doi = {10.1145/3503222.3507726}
}