一句话：提出利用77K快速导线的CPU流水线与片上网络微架构，使低温计算机系统性能提升3.82倍。
低温计算通过在极低温下运行设备，可显著降低导线电阻和漏电流，主存、缓存、CPU核等已有研究，但快速低温导线尚未被充分利用，而慢导线正成为现代处理器性能瓶颈。本文提出充分开发77K快速导线的CPU微架构。作者先建立并验证用于CPU流水线和片上网络NoC的低温性能模型，这些部件性能可受慢导线严重限制；基于模型分析，设计CryoSP流水线和CryoBus NoC。评估表明，采用两种微架构的低温计算机相对传统系统获得3.82倍系统级性能提升，其中CryoSP时钟频率提高96%，CryoBus将NoC延迟降至五分之一。
Cryogenic computing, which runs a computer device at an extremely low temperature, is promising thanks to its significant reduction of wire resistance as well as leakage current. Recent studies on cryogenic computing have focused on various architectural units including the main memory, cache, and CPU core running at 77K. However, little research has been conducted to fully exploit the fast cryogenic wires, even though the slow wires are becoming more serious performance bottleneck in modern processors. In this paper, we propose a CPU microarchitecture which extensively exploits the fast wires at 77K. For this goal, we first introduce our validated cryogenic-performance models for the CPU pipeline and network on chip (NoC), whose performance can be significantly limited by the slow wires. Next, based on the analysis with the models, we architect CryoSP and CryoBus as our pipeline and NoC designs to fully exploit the fast wires. Our evaluation shows that our cryogenic computer equipped with both microarchitectures achieves 3.82 times higher system-level performance compared to the conventional computer system thanks to the 96% higher clock frequency of CryoSP and five times lower NoC latency of CryoBus.