一句话：将分离编译与链接引入 FPGA 流程，使同一 C 代码秒级编译到处理器核、分钟级编译到 FPGA 区域，实现类似 -O0/-O1 的快速迭代。
FPGA 加速器在绝对性能和能效上优于通用 CPU，且如今可用 C 等标准语言描述，但其开发流程仍冗长且对软件工程师不友好：编译可能耗时数十小时，无法支撑现代软件工程所依赖的快速增量精化。为打破这一瓶颈，作者将分离编译（separate compilation）与链接引入 FPGA 设计流程，提供相应抽象、编译器选项与编译流程，使同一份 C 源码既能秒级编译到处理器核，也能分钟级编译到 FPGA 区域，从而补足软件开发中熟悉的 -O0 与 -O1 快速选项。该工作提升了 FPGA 的编程层次并标准化了编程体验，使 FPGA 加速器融入软件工程师更熟悉的软件平台生态。摘要以定性方式说明编译器速度量级，未报告详细实验数据。
FPGA-based accelerators are demonstrating significant absolute performance and energy efficiency compared with general-purpose CPUs. While FPGA computations can now be described in standard, programming languages, like C, development for FPGAs accelerators remains tedious and inaccessible to modern software engineers. Slow compiles (potentially taking tens of hours) inhibit the rapid, incremental refinement of designs that is the hallmark of modern software engineering. To address this issue, we introduce separate compilation and linkage into the FPGA design flow, providing faster design turns more familiar to software development. To realize this flow, we provide abstractions, compiler options, and compiler flow that allow the same C source code to be compiled to processor cores in seconds and to FPGA regions in minutes, providing the missing -O0 and -O1 options familiar in software development. This raises the FPGA programming level and standardizes the programming experience, bringing FPGA-based accelerators into a more familiar software platform ecosystem for software engineers.
@inproceedings{XiaoMBHAGMD22,
title = {PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development},
author = {Yuanlong Xiao and Eric Micallef and Andrew Butt and Matthew Hofmann and Marc Alston and Matthew Goldsmith and Andrew Merczynski-Hait and André DeHon},
booktitle = {ASPLOS},
year = {2022},
doi = {10.1145/3503222.3507740}
}