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P2 ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators

ShakeFlow:使用延迟不敏感接口组合子的函数式硬件描述
ASPLOS Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22023匹配度 1/10 · 该论文属于函数式硬件描述语言与电路组合子方向,虽与 PL 沾边,但未涉及用户核心关注的静态分析、LLM/Agent、浮点程序分析或贝叶斯程序分析,也没有 AI 与 PL 的交叉。引用 5 inbox
Sungsoo Han, Minseong Jang, Jeehoon Kang
crossref: 2026-09-12

AI 速览

一句话:提出 ShakeFlow,用延迟不敏感接口组合子在函数式硬件描述中组合 valid/ready 等电路。

函数式编程在硬件描述中的优势已被广泛认可,函数式硬件描述语言常借助 map、filter 等组合子支持电路的组合式描述。然而,将这类组合子方法用于具有延迟不敏感接口(如 valid/ready 接口)的复杂电路存在困难,因为其前向与后向端口形成环状依赖。ShakeFlow 针对这一问题,提出以延迟不敏感接口组合子进行函数式硬件描述,力图在保留组合子组合优势的同时处理 valid/ready 等接口的双向、环状连接。给出的摘要未展开具体实现、形式化细节与实验评估。

问题
如何将函数式编程中的组合子方法应用于带 valid/ready 等延迟不敏感接口的复杂硬件电路,并处理其前向与后向端口形成的环状依赖。
方法
提出 ShakeFlow,一种带延迟不敏感接口组合子的函数式硬件描述语言或方法;具体技术细节在给出的摘要中未展开。
评估
给出的摘要未提供评估信息。
原文摘要(Abstract)

Functional programming’s benefits for hardware description have long been recognized in the literature. In particular, functional hardware description languages provide combinators such as maps and filters to facilitate the compositional description of circuits. However, it is challenging to apply functional programming with combinators to complex circuits with latency-insensitive interfaces such as valid/ready interfaces due to the cyclic nature of their forward and backward ports.

链接与引用

DOI 原文 · PDF(开放获取) ·

BibTeX
@inproceedings{paperbot9996,
  title = {ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators},
  author = {Sungsoo Han and Minseong Jang and Jeehoon Kang},
  booktitle = {ASPLOS},
  year = {2023},
  doi = {10.1145/3575693.3575701}
}